A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits.

In this paper, we propose an algorithm to classify spurious transitions in the activity of a digital circuit as generated and propagated glitches during logic simulation. Using the activities obtained, we compute a criticality metric to identify the nets where glitch minimization techniques are likely to provide the maximum benefit. The proposed metric provides insight into which techniques are best suited for use in glitch reduction for a given circuit. This enables targeted application of glitch reduction techniques. Experiments with several glitch intensive benchmarks show a faster convergence within fewer iterations to solutions with reduced glitch activity. We validate this observation by using the proposed metric to guide the application of some glitch reduction techniques and quantify the resultant savings. The proposed algorithm can be seamlessly incorporated in modern event-driven logic simulators.