Low-Temperature Wafer Bonding for Three-Dimensional Wafer-Scale Integration

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)(2018)

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摘要
In this paper, we report a low-temperature wafer-to-wafer fusion bonding process whose maximum processing temperature is 300C and can potentially be further reduced to 250C. This low-temperature process would enhance the compatibility of the three-dimensional wafer-scale integration technology with the devices and with the temporary adhesive materials that might suffer from high-temperature FBEOL processes. Preliminary experiments are done with blanket 300mm wafers, and characterization results from SAM imaging and mechanical shear test are reported to evaluate the feasibility of the low-temperature fusion bonding process.
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关键词
Bonding,Wafer scale integration,Annealing,Silicon,Force,Wafer bonding
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