A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.

IEEE Journal of Solid-State Circuits(2019)

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摘要
A 6-bit 2.5-GS/s 8× dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifierstructured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-...
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关键词
Interpolation,Latches,Time-domain analysis,Calibration,Power demand,Capacitance,Analog-digital conversion
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