Constant Matrix Multiplication with Ternary Adders

Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. The CMM operation can be realized multiplierless using only additions/subtractions and bit shifts. Modern FPGAs support the efficient mapping of ternary adders, i.e., adders with three inputs. Previous work has shown that the usage of ternary adders for the FPGA implementation of other multiplierless constant multiplication problems is very beneficial. However, no algorithm exists to optimize CMM operations with ternary adders. This work proposes a novel heuristic approach to further reduce CMM complexity for FPGAs by exploiting ternary adders. The algorithm can be targeted for combinatorial CMM with minimal depth or fully pipelined CMM operations. It is shown experimentally that 30% less operations are needed on average by using ternary adders, resulting in 11% LUT reductions.