EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA

In recent years, Convolution Neural Network (CNN) gained great success in many applications, especially in computer vision. Now adapting CNN inference on edge devices has become an active research area in embedded vision and hot topic in Edge AI. The primary design hurdles for implementing CNN inference on embedded systems are limited computational resource, memory resource, and power budget. This study presents a novel architecture for SqueezeNet [1] like CNN models, which can be extended to support any CNN model as well. We address two approaches to mitigate resource constraints. First, we use a custom floating point(12 bit for computation and 8bit for storing). Second is slicing the model into a repetitive block called computation blocks. Computation block can be configured dynamically by the host processor to operate in a different mode. We have implemented SqueezeNet v1.1 for Image-Net [2] for large-scale classification which achieved around 9 FPS at 100MHz. SqueezeNet, mapped for our architecture achieves top-1 accuracy of 51% for the ImageNet dataset. Unlike other implementations which use FPGA boards with a large amount of resources, our experiments are done in DE10 Nano which mimics actual embedded system like environment.