On the ESD behavior of a-Si:H based thin film transistors: Physical insights, design and technological implications
2018 IEEE International Reliability Physics Symposium (IRPS)(2018)
摘要
In this work, we present detailed physical and technological insights into the ESD behavior of a-Si:H TFTs. Pre-Breakdown mechanism is investigated using Electron microscopy, Raman spectroscopy and on-the-fly I-V/ C-V measurements in between TLP stress. Competing mechanisms of device failure and effect of various performance parameters on failure threshold are investigated. Effect of channel dimensions on failure mechanism is thoroughly explored. For the first time, ESD behavior of a-Si:H display technology based Gated diodes and Resistors is reported. Detailed investigation on Drain Underlap devices and their possible usage as I/O protection device in a-Si:H technology is discussed.
更多查看译文
关键词
Amorphous silicon,Electrostatic Discharge,Thin film transistors,Degradation,Dielectric breakdown,Gated Diodes,Drain Underlap
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要