FPGA Implementation of A Hybrid Decoder for STT-MRAM

Process variation and random thermal fluctuation severely affect the reliability of spin-torque transfer magnetic random access memory (STT-MRAM). This paper presents an FPGA-based two-stage hybrid decoder of extended Hamming codes for STT-MRAM with less decoding latency and lower implementation complexity. Experiments indicate that the presented implementation can improve the STT-MRAM's tolerance to process variation and random thermal fluctuation.