Fast Statistical Modelling of Temperature Variation on 28 nm FDSOI Technology.

It is well known that the 28 nm fully depleted Silicon-On Insulator (FDSOI) node has a temperature effect due to the inherent pyroelectric and piezoelectric properties. In this paper, we introduce a spatial interpolation Lookup table (LUT) model considering temperature dependence of nanometer CMOS transistors. The novel methodology is used to build the bias current and capacitance LUTs for MOS transistor circuits under extensive variety of temperature values, evaluated under transient analysis. This innovative LUTs model significantly reduce the simulation runtime with sufficient accuracy using adaptive multivariate precomputed Barycentric relational interpolation for the appraisal temperature effects of 28 nm FDSOI node.