ILP-Based Modulo Scheduling and Binding for Register Minimization
FPL, pp. 265-271, 2018.
A key element for achieving high throughput, e.g. circuits generated with high-level synthesis (HLS) methods and model-based hardware design, is the use of modulo scheduling. Integer linear programming (ILP)-based modulo schedulers are capable of computing schedules that are optimal regarding throughput and latency, while keeping run time...More
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