Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis

FPL, pp. 280-286, 2018.

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Abstract:

Modulo scheduling is a key throughput optimisation when compiling for VLIW architectures, which has been applied successfully to high-level synthesis (HLS) of hardware accelerators in the past. However, problem instances in the HLS context usually have larger and denser dependence graphs and may contain many simple operations that are not...More

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