Bias Scheme Reducing Transient Currents and Speeding up Read Operations for 3-D Cross Point PCM

3-D cross point phase change memory (PCM) is a promising emerging memory. However, dynamic performances of 3-D cross point PCM are limited and the role of bias scheme is unknown. Previous studies on bias schemes for planar memories use static analyses to assess static array performances. Here, a high peak transient read current is found to result in a long read access time. Three factors which contribute to the high peak read current are analyzed. The proposed 2V/3 bias scheme and a single-reference parasitic-matching sensing circuit are utilized in a 64Mbit 3-D cross point PCM. The sensing time is reduced by 22.5 for the development of high-performance 3-D PCM technology to boost the working efficiency of computing systems. The following contents are the listed errors as mentioned in the comments for reasons of withdrawal: missing labels of Fig.1, lack of the explanation of the peak current on the sensing speed, lack of the reason of the chosen of 2V/3 scheme, lack of influence of the parasitic capacitors, unclear explanation of the factor that contributes to a high peak read current, lack of comparisons, lack of the explanation of the sneak current, lack of the explanations of the SRPM sensing circuit, lack of the define valuables like NM_A1, unclear explanation of comparisons of the power consumption, wrong writing of the two conventional circuits, writing of 3D-IC, wrong writing of number of memory layers, etc. These errors may confuse a good understanding of our work. Therefore, we decide to withdraw this manuscript from arXiv. We will significantly rewrite it and publish the correct and complete paper in the future.