Bancs: Bidirectional Alternating Nanomagnetic Clocking Scheme

The CMOS technology is reaching its physical limitations as the transistors' feature size decreases. The Nanomagnetic Logic (NML) field-coupled nanocomputing paradigm is one of the promissing alternatives for future nanotechnologies. NML utilizes single domain magnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS transistor due to the absence of static energy. An important issue when designing NML circuits is the thermal noise effect, which leads to errors when magnets are consecutively switched. In this paper we propose BANCS, a novel clocking scheme for the nanomagnetic logic technology. BANCS standardizes three-phase NML clocking system, and also minimizes the thermal noise effect. We have validated BANCS using three circuits: XOR gate, C17 ISCAS 85 benchmark, and Tougaw 4-bit ripple carry adder. We compare the area occupied by versions with and without our clock scheme. Our results show that although BANCS imposes area overhead, the scalability gain is a good tradeoff.