Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM.

Shouyi Yin,Tianyi Lu,Zhicong Xie,Leibo Liu,Shaojun Wei

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2018）

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摘要

Spin-transfer torque random access memory (STT-RAM) is one of the most promising emerging nonvolatile memory technologies suitable for substituting traditional memory due to its fascinating features, such as high density and low-leakage power. Multilevel cell (MLC) STT-RAM stores two or more bits in a single cell, which can boost data density. Memory partitioning is an efficient method to overcome...

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关键词

Arrays,Partitioning algorithms,Field programmable gate arrays,Optimization,Microprocessors,Buffer storage

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