Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis
IEEE Design & Test, pp. 54-62, 2018.
Computer bugsHardwareIP networksIntellectual propertyHardware design languages
This article presents an automated approach for detecting system- level bugs in SoC designs that are composed of many IP blocks, without exposing sensitive information. The approach leverages high-level synthesis techniques.
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