Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis

IEEE Design & Test, pp. 54-62, 2018.

Cited by: 2|Bibtex|Views7|Links
EI WOS
Keywords:
Computer bugsHardwareIP networksIntellectual propertyHardware design languages

Abstract:

This article presents an automated approach for detecting system- level bugs in SoC designs that are composed of many IP blocks, without exposing sensitive information. The approach leverages high-level synthesis techniques.

Code:

Data:

Your rating :
0

 

Tags
Comments