A 6-Wire Plug And Play Clockless Distributed On-Chip-Sensor Network In 28 Nm Utbb Fd-Soi

This paper describes a solution for SOC 'on-chip sensor' management exploiting the robustness of delay insensitive clockless logic. This low signal count, high bandwidth and variation insensitive solution, provides SOC architects a means to integrate on chip sensors (e.g., process monitor sensors), with a simplification of design integration and verification requirements. This is demonstrated by silicon measurements accessing sensors across the network for an ultra-wide voltage range 0.4 V-1.3 V.