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Clock Synchronous Reset and Skew Calibration of 65gs/s ADCs in A Multi-Lane Coherent Receiver

Shankarram Athreya,Hiva Hedayati, Shayan Kazemkhani,Yanfei Chen, Saurabh Vats,Michael D. Scott, Bart Zeydel, Peter Keller,Jian Wang, Bhaskarareddy Avula,Boris Murmann,Echere Iroaga

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)（2018）

Cited 3|Views6
Key words
time-interleaved ADC,clock synchronous reset,skew calibration,coherent receiver
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