A Recurrently Generated Overlay Architecture For Rapid Fpga Application Development
HEART 2018: PROCEEDINGS OF THE 9TH INTERNATIONAL SYMPOSIUM ON HIGHLY-EFFICIENT ACCELERATORS AND RECONFIGURABLE TECHNOLOGIES(2018)
摘要
Recent FPGA research has increasingly focused on overlays-virtual coarse-grained architectures-to address widely known application-design productivity problems such as lengthy compilation times and a lack of portability. However, existing overlay research has not yet been adopted due to several key limitations: 1) a general focus on datapath-centric applications with little control logic, and/or 2) manual creation of overlays for a given application or domain. Ideally, FPGA design tools would automatically generate specialized overlays for any application. In this paper, we present a first step towards this ideal goal by integrating datapath-centric overlays with finite-state-machine overlays, which we recurrently generate as application characteristics and resource requirements change during application development. By generating overlays capable of supporting arbitrary controllers and datapaths, our approach enables rapid development of numerous FPGA applications, while potentially providing a target architecture to enable high-level synthesis that is comparable in productivity to compilers for microprocessors and GPUs. We demonstrate that our proposed overlay architecture can enable compilation times that are over 100,000x faster than register-transfer-level designs, with overheads comparable to existing overlays. For iterative development, we show recurrent overlay generation provides faster development cycles than traditional FPGA development after only two design iterations, which improves further for additional iterations by amortizing overlay generation across multiple rapid virtual compilations and reconfigurations.
更多查看译文
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络