Design And Data Management For Magnetic Racetrack Memory
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)(2018)
摘要
Benefiting from its ultra-high storage density, high energy efficiency, and non-volatility, racetrack memory demonstrates great potential in replacing conventional SRAM as large on-chip memory. Integrating the tape-like racetrack memory, however, faces unique design challenges from cell structure to architecture design. This paper reviews some cross-layer design methodologies for racetrack memory as on-chip cache hierarchy. Research studies show that with proper architectural design and data management, racetrack memory can achieve significant area reduction, system performance enhancement, and energy saving compared to state-of-the-art memory technologies.
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关键词
cross-layer design methodologies,data management,magnetic racetrack memory,ultra-high storage density,high energy efficiency,on-chip memory,architectural design,memory technologies,tape-like racetrack memory,cell structure,on-chip cache hierarchy,system performance enhancement,energy saving
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