An Analog Visual Saliency Processor Using Time-Mode Computation

This paper presents an analog CMOS architecture for a visual saliency processor inspired by neuromorphic saliency algorithms. Time-mode computation is used to take advantage of the voltage-to-time conversion already present in many imager architectures so that the processor can be integrated directly into a CMOS imager. The architecture makes use of recent advances in time-mode computation, in particular the time-mode translinear principle, to realize the saliency algorithm with only pulse based computation. Simulation results are presented on a large image dataset, and a synthesis strategy is demonstrated. The circuit was implemented in a 45nm CMOS process, and post layout simulations are presented characterizing the circuit.