An Automated SerDes Frontend Generator Verified with a 16nm Instance Achieving 15 Gb/s at 1.96 pJ/bit

In this paper we present an automated SerDes frontend generator along with experimental results from an instance produced in TSMC 16nm. The generator is an automated, parameterized design procedure that produces schematics and layouts based on top level performance and architecture specifications. A DDR current-integration SerDes instance was generated in TSMC 16nm technology with passive CTLE, 1-tap FFE, and 4-tap DFE equalization. The instance operates at 15 Gb/s with BER < 1E-12, and consumes 29.4 mW (1.9 pJ/bit) from 0.8V/0.9V supplies.