A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers.

Rohan Sehgal,Frank M. L. van der Goes,Klaas Bult

IEEE Journal of Solid-State Circuits（2018）

引用 37|浏览3

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摘要

A 12-bit pipelined analog-to-digital converter (ADC) using a new integration-based open-loop residue amplifier topology is presented. The amplifier distortion is cancelled with the help of an analog linearization technique based on a tunable input-driven active degeneration. Amplifier gain and nonlinearity errors are detected in background using split-ADC calibration technique. The mismatch betwee...

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关键词

Calibration,Jitter,Signal to noise ratio,Clocks,Linearization techniques,Transistors

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