Optimizing Cache Bypassing and Warp Scheduling for GPUs.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2018)

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摘要
The massive parallel architecture enables graphics processing units (GPUs) to boost performance for a wide range of applications. Initially, GPUs only employ scratchpad memory as on-chip memory. Recently, to broaden the scope of applications that can be accelerated by GPUs, GPU vendors have used caches as on-chip memory in the new generations of GPUs. Unfortunately, GPU caches face many performanc...
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关键词
Instruction sets,Graphics processing units,Pipelines,Computer architecture,System-on-chip,Parallel processing,Registers
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