Detection Of Ijtag Attacks Using Ldpc-Based Feature Reduction And Machine Learning

2018 23RD IEEE EUROPEAN TEST SYMPOSIUM (ETS)(2018)

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摘要
IEEE 1687 standard (IJTAG), as an extension to the IEEE 1149.1, facilitates efficient access to embedded instruments by supporting reconfigurable scan networks. Specifically, IJTAG allows each IP to be wrapped by a test data register (TDR) whose access is controlled by a segment insertion bit (SIB) or a scan-mux control bit (SCB). Because the TDRs and the SIB/SCB network are typically not public, but critical for accessing embedded instruments, they might be used for illegitimate purposes, such as dumping credential data and reverse engineering IP design. Machine learning has been proposed to detect such attacks, but the large number of instruments and parallel execution enabled by the IJTAG produce high-dimensional data, which poses a challenge to on-chip detection. In this paper, we propose to reduce the high-dimensional but sparse data using a low-density parity-check (LDPC) matrix. Experiments using a modified version of the OpenSPARC T2 to include IJTAG functionality demonstrate that the use of feature reduction eliminates 91% of the features, leading to 43% reduction in circuit size without affecting detection accuracy. Also, the on-chip detector adds moderate overhead (similar to 8%) to the IJTAG.
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关键词
machine learning,high-dimensional data,on-chip detection,high-dimensional but sparse data,low-density parity-check matrix,IJTAG functionality,detection accuracy,IJTAG attacks,LDPC-based feature reduction,IEEE 1687 standard,IEEE 1149,embedded instruments,reconfigurable scan networks,segment insertion bit,scan-mux control bit,SIB/SCB network,credential data,test data register,reverse engineering IP design
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