Reducing the amount of transistors by gate merging

It is presented a method to reduce the amount of transistors by doing gate merging. It is also introduced a tool called LOMGAM that does Logic Minimization by Gate Merging. It is generated complex gates by the merging of a set of basic gates with unitary fan out. It is also controlled the number of serial transistors in Pull Up and Pull Down networks. The LOMGAM also control the number of inverters that can be added in the circuit. It was executed LOMGAM for the ITC 99 and ISCAS 99 benchmarks. It is presented a quantitative analysis in terms of the number of transistors and interconnections. In average, the reduction on number of transistors is 14,47% and the reduction on the number of interconnections is 28,41%.