Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing

Highly compact as well as compressed test pattern generation may result in the aggregation of high power activity in specific areas on a manufactured circuit during testing. These hotspots can lead to electromigration and IR-drop in local blocks of the chip resulting in wrong test results. This is due to the circumstance that the effect of localized high switching activity is not precisely taken into consideration during ATPG and pattern simulation. Discarding such patterns may result in test coverage loss. Low power test generation methods typically reduce the switching activity globally across the pattern and not locally in specific areas. Additionally, these methods typically increase the test data volume as well as the testing time. In this paper, a test pattern retargeting methodology is proposed which takes pattern-specific, dynamically identified hotspots into account. Critical patterns and their corresponding critical regions are identified. Based on this data, constraints are used for pattern retargeting preventing the previously identified local hotspots. In contrast to previous methods, the proposed retargeting technique ensures a high test coverage without a large pattern inflation.