A Low Power Tdc With 0.5ps Resolution For Adpll In 40nm Cmos
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)(2015)
摘要
A low power time-to-digital converter (TDC) with high resolution is presented in this paper. The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a phase-prediction technique. A snapshot circuit is used to reduce the sampling rate from digitally-controlled oscillator (DCO) frequency to reference frequency, thus greatly saving power. In addition, the proposed digital architecture adopts a time-amplifier based TDC (TA-TDC) to achieve high resolution. The proposed TDC is implemented in SMIC 40nm CMOS. Simulation results show that it can achieve a resolution about 0.5ps while totally consuming only 163uW.
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关键词
time-to-digital converter, all-digital PLL, digital-to-time converter, time amplifier
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