Reliability Concerns On Time-To-Digital Converter Due To Bias Temperature Instability In Nanometer Era

The integrated circuit (IC) performance degradation is increasing in nanometer era. IC lifetime performance enhancement design techniques rely on chip lifespan simulation and predictive techniques. In this paper, we show a time to digital converter (TDC) circuit performance degradation simulation and predictive diagnosis method due to negative bias temperature instability. The performance degradation testing is based on comparing a reference TDC circuit with one performance degradation tracking TDC circuit. The TDC performance degradation is decided by the resolution time of inverter chain due to the threshold voltage Vth variation. For alleviating the impact of process variation, the performance degradation circuit employs large size. Design and simulation are based on TSMC 180nm process technology. The simulation results are based on the estimation of the threshold voltage shift for negative bias temperature instability effect. The delay error of TDC due to negative bias temperature instability effect in 6 years is 6% in 180nm technique and 100 degrees C. Thus, the simulation and predictive diagnosis method proposed in this paper can effectively save large design margin further save cost design cost.