Hybrid-Comp: A Criticality-Aware Compressed Last-Level Cache
2018 19TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)(2018)
摘要
Cache compression is a promising technique to increase on-chip cache capacity and to decrease off-chip bandwidth usage. While prior compression techniques always consider a trade-off between compression ratio and decompression latency, they are oblivious to the variation in criticality of different cache blocks. In multi-core processors, last-level cache (LLC) is logically shared but physically distributed among cores. In this work, we demonstrate that, cache blocks within such non-uniform architecture exhibit different sensitivity to the access latency. Owing to this behavior, we propose a criticality-aware compressed LLC that favors lower latency over higher capacity based on the criticality of the data blocks. Based on our studies on a 16-core processor with 4MB LLC, our proposed criticality-aware mechanism improves the system performance comparable to that of with an 8MB uncompressed LLC.
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关键词
promising technique,on-chip cache capacity,off-chip bandwidth usage,different sensitivity,criticality-aware compressed LLC,data blocks,16-core processor,criticality-aware mechanism,last-level cache compression,memory size 4.0 MByte,memory size 8.0 MByte
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