An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2018）

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摘要

This paper presents a new electrical-based stress model that addresses the stress effect in the nanometer CMOS devices. As such, the electrical performance of analog circuits in the presence of stress can be better predicted in statistical simulations. The model provides a random stress-induced offset. It relies on the current-resistance product-based random generators, which have the feature of G...

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关键词

Stress,Semiconductor device modeling,MOSFET,Performance evaluation,Integrated circuit modeling,Predictive models

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