Gate elimination: Circuit size lower bounds and #SAT upper bounds.

Theor. Comput. Sci.(2018)

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摘要
Most of the known lower bounds for binary Boolean circuits with unrestricted depth are proved by the gate elimination method. The most efficient known algorithms for the #SAT problem on binary Boolean circuits use similar case analyses to the ones in gate elimination. Chen and Kabanets recently showed that the known case analyses can also be used to prove average case circuit lower bounds, that is, lower bounds on the size of approximations of an explicit function.
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关键词
Circuit complexity,Lower bounds,Exponential time algorithms,Satisfiability
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