A Heterogeneous Parallel Processor for High-Speed Vision Chip.

IEEE Transactions on Circuits and Systems for Video Technology(2018)

引用 23|浏览42
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摘要
This paper proposes a heterogeneous parallel processor for high-speed vision chip. It contains four levels of processors with different parallelisms and complexities: processing element (PE) array processor, patch processing unit (PPU) array processor, self-organizing map (SOM) neural network processor, and dual-core microprocessor unit (MPU). The fine-grained PE array processor, middle-grained PP...
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关键词
Feature extraction,Parallel processing,Arrays,Neurons,Computer vision
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