A 23.6mb/Mm(2) Sram In 10nm Finfet Technology With Pulsed Pmos Tvc And Stepped-Wl For Low-Voltage Applications

The emergence of cloud computing and big data analytics, accompanied by a sustained growth of battery-powered mobile devices, continues to drive the importance of energy and area efficient CPU and SoC designs. Low-voltage operation remains one of the primary approaches for active power reduction, but SRAM l/ MIN can limit the minimum operating voltage. Device size quantization continues to be a challenge for compact 6T SRAM design in FinFET technologies, where careful co-optimization of the technology and assist circuit design is required for high-density low-voltage array implementations. This paper presents two SRAM array designs in a 10nm low-power CMOS technology featuring 3 rd generation FinFET transistors: a high-density 23.6Mb/mm 2 array and a low-voltage 20.4Mb/mm 2 array.