A Framework for Generating High Throughput CNN Implementations on FPGAs

    FPGA, pp. 117-126, 2018.

    Cited by: 41|Bibtex|Views27|Links
    EI

    Abstract:

    We propose a framework to generate highly efficient accelerators for inferencing on FPGAs. Our framework consists of multiple algorithmic optimizations for computation complexity and communication volume reduction, a mapping methodology for efficient resource utilization, and a tool for automatic \textttVerilog generation. The algorithmi...More

    Code:

    Data:

    Your rating :
    0

     

    Tags
    Comments