A Framework for Generating High Throughput CNN Implementations on FPGAs
FPGA, pp. 117-126, 2018.
We propose a framework to generate highly efficient accelerators for inferencing on FPGAs. Our framework consists of multiple algorithmic optimizations for computation complexity and communication volume reduction, a mapping methodology for efficient resource utilization, and a tool for automatic \textttVerilog generation. The algorithmi...More
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