Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform

Collision detection algorithms are used to detect when virtual objects collide with one another and calculate the results of these collisions. These types of algorithms are, typically, critical real-time calculations needed for applications such as simulation, tolerance checking, and video games. In this work, we present an implementation of the smallest piece of a collision detection pipeline implemented on Intel's Heterogeneous CPU-FPGA Platform. This platform includes both an FPGA and CPU that allows real-time processing of fine grained applications such as collision detection. We present a heterogeneous implementation that uses the FPGA to accelerate a particular collision detection stage as an accelerated part of a complete collision detection pipeline on a real system to demonstrate how collision detection can benefit from co-processing even in its worst-case implementation. We believe as Intel continues to integrate FPGAs with processors on a single die that algorithms like these need to be both optimized and open sourced to the general computing community ¹ so that they can be included and studied as part of a full simulation system where the GPU is dedicated to graphics and the CPU cores to world management. In our case, our results show a speedup of 14.81% with the FPGA as compared to a CPU only implementation. The importance of this result is that it demonstrates that even the worst implementation in terms of data communication to computation ratio for collision detection on a real heterogeneous system can be used as an accelerator, and more importantly, this is the starting point for researchers to investigate where these algorithms should be located in the system whether on the traditional CPU cores, the GPU, or a co-processing FPGA.