Synthesis of interleaved multithreaded accelerators from OpenMP loops

ReConFig, pp. 1-7, 2017.

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Abstract:

Similarly to CPUs and GPUs, FPGA-based accelerators can also profit from exploiting thread-level parallelism. Thus, the synthesis tools for generating the circuits from high-level languages need to be extended appropriately. We present an extension of the Nymble hardware/software-co-compiler for the automatic synthesis of hardware acceler...More

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