TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 231-244, 2018.
As very large scale integration technology scales to deep submicrometer and beyond, interconnect delay greatly limits the circuit performance. The traditional 2-D global routing and subsequent net by net assignment of available empty tracks on various layers lacks a global view for timing optimization. To overcome the limitation, this pap...More
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