A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI

We propose a column-based split cell-VSS (CS-CVSS) data-aware write-assisted (DAW A) 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI technology. The proposed write-assist technique (CS-CVSS and DAWA) improve both half-select SNM and write margin. The proposed 3T low leakage read port enhances read sensing margin by minimizing bitline leakage through negative gate to source voltage. A 16kb 9T SRAM test chip demonstrates VDDMIN-Write improvement of 0.39 V and VDDMIN-Read of 0.25 V with 1.57 ps read access time. The energy of 6.72 pJ is achieved at 0.5 V.