Optimal design flow of CMOS doubler-based rectifiers

This paper proposes an optimal design flow for designing CMOS doubler based rectifiers. The work uses a simulation-based approach, considering important bounds on the size of the components. A way for comparing and predicting the performance of diodes made of various devices has been presented. The flow is specifically shown in the context of Radio-Frequency (RF) energy harvesting application. However the flow can be also extended to other application scenarios. The design flow is explained using diode characteristics and is independent of the device and technology used to make the diode. The flow has been demonstrated by comparing doubler-based rectifiers designed with this flow with two earlier works in 180nm CMOS technology. In one case the power delivered to the load has increased more than 1.8 times, and in the other case the area is 2/3 of the area used in the previous work.