Switch cell optimization of power-gated modern system-on-chips.

This work addresses a practical problem of allocating and placing a minimal number of active switch cells in power gated modern System-on-Chips (SoCs) to save the unnecessary standby leakage under noise (i.e., IR-drop) constraint. Since power gating switch cells are physically directly connected to power rails, their overall allocation structure is synthesized in a stage before the logic cell placement. Consequently, the allocation of switch cells in the pre-placement could lead to unnecessarily high standby leakage for modern designs. This work proposes a practical remedy for this problem at the post-placement stage. Specifically, for an initial design with a grid-based switch cell allocation, which is commonly used design methodology in industry, we propose a comprehensive solution to determining, for each switch cell, (1) whether the cell can be permanently turned off or (2) the type of switch cell for replacement so that the resulting total standby leakage of switch cells should be minimized under the noise constraint. We formulate the problem into a variant of weighted set cover problem and solve it efficiently by employing an approximate set cover algorithm. Through experiments with benchmark circuits in ISCAS89, openMSP430, and fpu, it is shown that our method is able to reduce the standby leakage by 35.0% and 13.9% over the initial designs and the designs produced by the previous switch cell optimization method in [5], respectively.