PhD forum: Heterogeneous interconnection of ICs using stitch-chips

In this paper, a heterogeneous interconnect stitching technology (HIST) is presented. Stitch chips with high-density fine pitch wires are used to connect active dice of various functions in a manner that mimics system-on-chip (SoC) like performance. Microbumps and compressible microinterconnects (CMIs) are used to provide die-to-die and die-to-package interconnection. A testbed containing two dummy dice and one stitch chip is fabricated and tested. The average measured post-assembly resistance of the microbumps and the CMIs is 116.5 μΩ and 195.9 mμ, respectively. Using an electrical model for HIST signal channels, a 50%-50% delay as small as 140 ps with an energy efficiency of 0.24 pJ/bit may be achieved for a 1mm channel. In addition, some power delivery challenges and opportunities of HIST are highlighted through simulations. The results show that compared to interposer based 2.5-D integration, HIST may reduce the IRdrop by approximately 18.4%.