A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer.

This paper proposes a 40-nm CMOS 2×VDD buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both nMOS and pMOS could be detected. Thus, the SR deviations will be significantly reduced by controlling the switches of the output stage accordingly. Besides, leakage reduction circuit wil...