Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology.

Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with...