A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.

Jay Im,Dave Freitas,Arianne Roldan,Ronan Casey,Stanley Chen,Adam Chou,Tim Cronin,Kevin Geary,Scott McLeod,Lei Zhou,Ian Zhuang,Jaeduk Han,Sen Lin,Parag Upadhyaya,Geoff Zhang,Yohan Frans,Ken Chang

IEEE Journal of Solid-State Circuits（2017）

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摘要

A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifie...

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关键词

Decision feedback equalizers,Decision feedback equalizers,Amplitude modulation,Power demand,FinFETs,Bit error rate,Standards

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