A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures

Binary Edwards Curves (BEC) constitute an alternative to the standardized Weierstrass elliptic curve (EC) equations since the latter have intrinsic side channel attack vulnerabilities due to their lack of point operation uniformity. Thus, BECs have gained popularity over the past few years due to their uniformity, operation regularity, completeness and implementation attractiveness. However, BEC Scalar multiplication hardware implementations are still lacking in performance when compared to their Weierstrass equivalent. In this paper, a design strategy/methodology is proposed in order to realizeBEC Scalar multipliers with a good trade-off between computation speed and utilized hardware resources. The strategy is based on a GF(2k) operations parallelism mechanism that aims at the minimization of idle states in the utilized processing elements as well as the minimization of employed storage andcontrol elements. A BEC SM architecture is proposed in order to describe the realization of the proposed strategy and its benefits are analyzed. In order to evaluate the efficiency of the proposed architecture an implementation was made in FPGA technology for GF(2^233) fields with BECs using d1 = d2. Whencompared to other works, the implementation expressed very balanced results.