A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.

P. Salz, A. Frisch,Wolfgang Penth, J. Noack, T. Kalla,Rolf Sautter,Michael Kugel,Otto A. Torreiter, G. Sapp,M. Lee,Eric Fluhr, A. Rozenfeld,Jürgen Pille,Dieter F. Wendel

ESSCIRC 2017 - 43RD IEEE EUROPEAN SOLID STATE CIRCUITS CONFERENCE（2017）

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摘要

The POWER9 (TM) Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fast and low-latency write assist schemes for single voltage performance arrays, as well as a new methodology, the synthesized soft arrays, to enable significant improvements for small array structures in both area and design efficiency.

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关键词

array families,synthesized soft arrays,processor generation,single-voltage performance arrays,array structures,SOI FinFET technology,POWER9 processor,low-latency write assist schemes,size 14.0 nm

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