Column-wise ROIC design with on-chip calibration for photoresistive image sensor
2017 European Conference on Circuit Theory and Design (ECCTD)(2017)
摘要
This paper describes a novel readout integrated circuit (ROIC) for a photoresistive image sensor array incorporating wheatstone bridge configuration with a variable-gain switched-capacitor amplifier. A 12-bit R-2R ladder digital-to-analog converter (DAC) is used for on-chip calibration. The bias voltage of the bridge is supplied by an on-chip DAC and made programmable between 0 to 1.8 Volts for ROIC performance optimization. This image sensor and ROIC system is intended to be used as an endoscope camera which demands strict silicon area and low power consumption requirements. A sample 1×16 line sensor is used for proof of concept. The ROIC is designed for the target of 30 frames per second output data rate for a 400×1 line sensor. This work focuses on the analog signal processing chain of the ROIC. The column-wise design makes the ROIC scalable for larger image sensor sizes. The nominal (base) resistance of each detector is assumed to have a variation of (±10%). The proposed ROIC is designed in 0.18μm CMOS process and the system is verified with post-layout simulations.
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关键词
column-wise ROIC design,on-chip calibration,readout integrated circuit,line sensor,photoresistive image sensor array,Wheatstone bridge configuration,R-2R ladder digital-to-analog converter,endoscope camera,analog signal processing chain,CMOS process,post-layout simulations,low power consumption requirements,ROIC performance optimization,on-chip DAC,variable-gain switched-capacitor amplifier,size 0.18 mum,word length 12 bit,voltage 0 V to 1.8 V,Si
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