Towards write-back aware software emulator for non-volatile memory

Non-volatile memory (NVM) such as phase change memory is a promising technology for future low-energy and high-capacity memory systems. One of the well-known issues of NVM is its fundamental characteristics that are different from common memory subsystems with DRAM. In particular, the NVM write latency is much higher than DRAM while the NVM read latency is almost the same as DRAM. The latency asymmetry affects the performance of applications significantly. For analyzing behavior of applications running on NVM environments, most researchers use emulation tools due to the limited number of commercial NVM products. However, these existing tools are too slow to emulate a large-scale workload or too simplistic to emulate the application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation model that is not only light-weight but also aware of the NVM read/write latency gap. We implemented our prototype on a commercial Intel processor. We also evaluated its accuracy and performed case studies for practical benchmarks. The results show that our prototype can emulate the execution time of practical workloads according to their write behavior, while an existing light-weight emulation model over-estimates the execution time.