ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning
2017 IEEE International Conference on Computer Design (ICCD)(2017)
摘要
As semiconductor technology advances, leading-edge product companies must rapidly improve yield for designs that seek to reach mass production while early in the adoption of a new technology node; otherwise, products may be unviable in the marketplace. In this paper, we are the first to study the possible mitigation by opportunistic, last-stage redundant logic insertion to mitigate yield loss in early advanced-node production. We describe a yield estimation methodology, and propose an integer linear programming (ILP)-based optimization of redundant logic insertion for opportunistic yield optimization. In our approach, we first identify potential logic clusters for replication by top-down application of multilevel FM partitioning. We then select promising clusters whose replication maximizes design yield without hurting design timing. Our experimental results show the potential for significant yield improvement with minor timing impact.
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关键词
VLSI,EDA,yield,advanced node,redundancy,physical design,ECO,clustering
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