DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systems.
MEMSYS 2017: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS(2017)
摘要
The implicit sharing of DRAM and other hardware resources among cores in COTS multi-core platforms results in interferences impeding safety, as guaranteed execution and timing predictability of tasks cannot be ensured. This paper presents a snapshot of the state-of-the-art to mitigate the impact of DRAM-related inter-core interferences and provides suggestions for DRAM-related challenges.
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关键词
Safety-critical systems,COTS multi-cores,COTS DRAM controller,timing predictability,inter-core interference
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