A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.

A highly digital two-stage fractional-N phaselocked loop (PLL) architecture utilizing a first-order 1-bit ΔΣ frequency-to-digital converter (FDC) is proposed and implemented in a 65nm CMOS process. Performance of the first-order 1-bit ΔΣ FDC is improved by using a phase interpolatorbased fractional divider that reduces phase quantizer input span and by using a multiplying delay-locked loop that in...